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HS-2420RH
July 1995
Radiation Hardened Fast Sample and Hold
Description
The HS-2420RH is a radiation hardened monolithic circuit consisting of a high performance operational amplifier with its output in series with an ultra-low leakage analog switch and MOSFET input unity gain amplifier. With an external hold capacitor connected to the switch output, a versatile, high performance sample-and-hold or track-andhold circuit is formed. When the switch is closed, the device behaves as an operation amplifier, and any of the standard op amp feedback networks may be connected around the device to control gain, frequency response, etc. When the switch is opened the output will remain at its last level. Performance as a sample-and-hold compares very favorably with other monolithic, hybrid, modular, and discrete circuits. Accuracy to better than 0.01% is achievable over the temperature range. Fast acquisition is coupled with superior droop characteristics, even at high temperatures. High slew rate, wide bandwidth, and low acquisition time produce excellent dynamic characteristics. The ability to operate at gains greater than 1 frequently eliminates the need for external scaling amplifiers. The device may also be used as a versatile operational amplifier with a gated output for applications such as analog switches, peak holding circuits, etc.
Features
* Maximum Acquisition Time - 10V Step to 0.1%. . . . . . . . . . . . . . . . . . . . . . . . . . . 4s - 10V Step to 0.01%. . . . . . . . . . . . . . . . . . . . . . . . . . 6s * Maximum Drift Current . . . . . . . . . . . . . . . . . . . . . .10nA (Maximum Over Temperature) * TTL Compatible Control Input * Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . .80dB * Total Gamma Dose. . . . . . . . . . . . . . . . . 1 x 105 RAD(SI) * No Latch-Up
Applications
* Data Acquisition Systems * D to A Deglitcher * Auto Zero Systems * Peak Detector * Gated Op Amp
Ordering Information
PART NUMBER HS1-2420RH-Q TEMPERATURE RANGE -55oC to +125oC PACKAGE 14 Lead CerDIP
Pinout
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE (CerDIP) MIL-STD-1835, GDIP1-T14 TOP VIEW
IN- 1 IN+ 2 14 SAMPLE/HOLD CONTROL 13 GND 12 NC 14 Pin DIP 11 HOLD CAPACITOR 10 NC 9 V+ 8 NC
Functional Diagram
OFFSET ADJUST 3 4 V+ 5
- INPUT
+ INPUT
1 + 2
-
+
-
7 OUTPUT
OFFSET ADJUST 3 OFFSET ADJUST 4 V- 5 NC 6 OUTPUT 7
14 SAMPLE/ HOLD CONTROL
HS-2420RH
13 5 11 GND VHOLD CAPACITOR
NOTE: Pin Numbers Correspond to DIP Package Only.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com | Copyright (c) Intersil Corporation 1999
Spec Number File Number
1
518855 3554.1
Specifications HS-2420RH
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . +40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V Digital Input Voltage (S/H Pin) . . . . . . . . . . . . . . . . . . . . . .+8V, -15V Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected Storage Temperature Range . . . . . . . . . . . . . .-65oC < TA < +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +275oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Reliability Information
Thermal Resistance JA JC CerDIP Package . . . . . . . . . . . . . . . . . . . 74oC/W 18oC/W Maximum Power Dissipation at +125oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W If Device Power Exceeds Package Dissipation Capability, Derate Linearly at the Following Rate CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mW/oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . .-55oC < TA < +125oC Operating Supply Voltage ( VSUPPLY) . . . . . . . . . . . . . . . . . . . 15V Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V Logic Level Low (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V Logic Level High (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 5.0V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified GROUP A SUBGROUPS 1 2, 3 Input Bias Current IB+ 1 2, 3 IB1 2, 3 Input Offset Current IIO 1 2, 3 Open Loop Voltage Gain +AVS RL = 2k, CL = 50pF, VOUT = +10V RL = 2k, CL = 50pF, VOUT = -10V V+ = 25V, V- = -5V, VOUT = +10V, VS/H = 10.8V V+ = 5V, V- = -25V, VOUT = -10V, VS/H = 9.2V VOUT = +10V VOUT = -10V RL = 2k, CL = 50pF 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 1 1 2, 3 -VOP RL = 2k, CL = 50pF 1 2, 3 Power Supply Current +ICC -ICC Power Supply Rejection Ratio +PSRR V+ = 10V and 20V, V- = -15V and -15V V+ = 15V and 15V, V- = -10V and -20V 1 1 1 2, 3 1 2, 3 LIMITS TEMPERATURE +25oC -55oC, -55oC, +125oC +125oC +25oC +25oC -55oC, +125oC +25oC -55oC, +125oC +25oC -55oC, +125oC +25oC -55oC, +125oC +25oC -55oC, +125oC +25oC -55oC, +125oC +25oC +25oC +25oC -55oC, +125oC +25oC -55oC, +125oC +25oC +25oC +25oC -55oC, +125oC +25oC -55oC, +125oC MIN -4 -6 -200 -400 -200 -400 -50 -100 25 25 25 25 80 80 80 80 +15.0 -15.0 +10.0 -10.0 -3.5 80 80 80 80 MAX 4 6 200 400 200 400 50 100 -10.0 -10.0 5.5 UNITS mV mV nA nA nA nA nA nA kV/V kV/V kV/V kV/V dB dB dB dB mA mA V V V V mA mA dB dB dB dB
PARAMETER Input Offset Voltage
SYMBOL VIO
CONDITIONS
-AVS
Common Mode Rejection Ratio
-CMRR
+CMRR
Output Current
+IO -IO
Output Voltage Swing
+VOP
-PSRR
Spec Number 2
518855
Specifications HS-2420RH
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified GROUP A SUBGROUPS 1 2, 3 IIN2 VIN2 = 5.0V 1 2, 3 Digital Input Voltage VIL 1 2, 3 VIH 1 2, 3 Drift Current ID VIN = 0V, RL = 2k, CL = 50pF, S/H = 4.0V 2 LIMITS TEMPERATURE +25oC -55oC, -55oC, +125oC +125oC +25oC +25oC -55oC, +125oC +25oC -55oC, +125oC +125oC MIN 2.0 2.0 -10 MAX 800 800 20 20 0.8 0.8 10 UNITS A A A A V V V V nA
PARAMETER Digital Input Current
SYMBOL IIN1
CONDITIONS VIN1 = 0V
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample), VIH = 2.0V (Hold), CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified GROUP A SUBGROUP 9 9 9 9 9 9 9 LIMITS TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN -20 3.5 3.5 MAX 20 100 100 40 40 UNITS mV ns ns % % V/s V/s
PARAMETER Hold Step Error Transient Response Rise Time and Fall Time Transient Response Overshoot Transient Response Slew Rate NOTE:
SYMBOL VERROR TR(TR) TR(TF) TR(+OS) TR(-OS) TR(+SR) TR(-SR)
CONDITIONS VS/H = 0V and 4V, tRISE (VS/H) 30ns (Note 1) CL = 50pF, RL = 2k, AV = +1, VOUT = 200mVP-P CL = 50pF, RL = 2k, AV = +1, VOUT = 200mVP-P CL = 50pF, RL = 2k, AV = +1, VOUT = 10VP-P
1. VERROR = VOUT (VS/H = 0V) - VOUT (VS/H = 4V) TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample), VIH = 2.0V (Hold), CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified LIMITS PARAMETER Hold Mode Feedthrough Attenuation Gain Bandwidth Product Acquisition Time (0.1%) SYMBOL VATTEN GBWP +tACQ (0.1%) -tACQ (0.1%) Acquisition Time (0.01%) CONDITIONS RL = 2k, CL = 50pF, AV = +1, VIN = 20VP-P, fIN = 50kHz RL = 2k, CL = 50pF, AV = +1, VIN = 100mVP-P RL = 2k, CL = 50pF, AV = +1, VOUT = 0V and +10V RL = 2k, CL = 50pF, AV = +1, VOUT = 0V and -10V NOTE 1 1 1 1 1 1 TEMPERATURE +25oC, -55oC, +125oC +25oC +25oC +25oC +25oC +25oC 2.5 4 4 6 6 MHz s s s s MIN 70 MAX UNITS dB
+tACQ (0.01%) RL = 2k, CL = 50pF, AV = +1, VOUT = 0V and +10V -tACQ (0.01%) RL = 2k, CL = 50pF, AV = +1, VOUT = 0V and -10V
NOTE: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics.
Spec Number 3
518855
Specifications HS-2420RH
TABLE 4. DC ELECTRICAL PERFORMANCE CHARACTERISTICS POST 100KRAD Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified GROUP A SUBGROUPS 1 1 1 1 RL = 2k, CL = 50pF, VOUT = +10V RL = 2k, CL = 50pF, VOUT = -10V V+ = 25V, V- = -5V, VOUT = +10V, VS/H = 10.8V V+ = 5V, V- = -25V, VOUT = -10V, VS/H = 9.2V VOUT = +10V VOUT = -10V RL = 2k, CL = 50pF 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 1 1 2, 3 -VOP RL = 2k, CL = 50pF 1 2, 3 Power Supply Current +ICC -ICC Power Supply Rejection Ratio +PSRR V+ = 10V and 20V, V- = -15V and -15V V+ = 15V and 15V, V- = -10V and -20V VIN1 = 0V 1 1 1 2, 3 1 2, 3 1 2, 3 IIN2 VIN2 = 5.0V 1 2, 3 Digital Input Voltage VIL 1 2, 3 VIH 1 2, 3 Drift Current ID VIN = 0V, RL = 2k, CL = 50pF, S/H = 4.0V 2 LIMITS TEMPERATURE +25oC +25oC +25oC +25oC +25oC -55oC, +125oC MIN -6 -400 -400 -100 25 25 25 25 80 80 80 80 +12.0 -12.0 +10.0 +10.0 -3.5 80 80 80 80 2.0 2.0 -10 MAX 6 400 400 100 -10.0 -10.0 5.5 800 800 20 20 0.8 0.8 10 UNITS mV nA nA nA kV/V kV/V kV/V kV/V dB dB dB dB mA mA V V V V mA mA dB dB dB dB A A A A V V V V nA
PARAMETER Input Offset Voltage Input Bias Current
SYMBOL VIO IB+ IB-
CONDITIONS
Input Offset Current Open Loop Voltage Gain
IIO +AVS
-AVS
+25oC -55oC, +125oC
Common Mode Rejection Ratio
-CMRR
+25oC -55oC, +125oC +25oC -55oC, +125oC
+CMRR
Output Current
+IO -IO
+25oC +25oC +25oC -55oC, +125oC
Output Voltage Swing
+VOP
+25oC -55oC, +125oC +25oC +25oC +25oC -55oC, +125oC
-PSRR
+25oC -55oC, +125oC
Digital Input Current
IIN1
+25oC -55oC, +125oC +25oC -55oC, +125oC
+25oC -55oC, +125oC
+25oC -55oC, +125oC
+125oC
Spec Number 4
518855
Specifications HS-2420RH
TABLE 4A. AC ELECTRICAL PERFORMANCE CHARACTERISTICS POST 100KRAD Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample), VIH = 2.0V (Hold), CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified LIMITS PARAMETER Hold Step Error SYMBOL VERROR CONDITIONS VS/H = 0V and 4V, tRISE (VS/H) 30ns (Note 1) CL = 50pF, RL = 2k, AV = +1, VOUT = 200mVP-P CL = 50pF, RL = 2k, AV = +1, VOUT = 200mVP-P CL = 50pF, RL = 2k, AV = +1, VOUT = 10VP-P GROUP A SUBGROUP 9 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN -20 MAX 20 UNITS mV
Transient Response Rise Time and Fall Time Transient Response Overshoot Transient Response Slew Rate NOTE:
TR(TR) TR(TF) TR(+OS) TR(-OS) TR(+SR) TR(-SR)
9 9 9 9 9 9
2.0 2.0
100 100 40 40 -
ns ns % % V/s V/s
1. VERROR = VOUT (VS/H = 0V) - VOUT (VS/H = 4V)
TABLE 5. BURN-IN DELTA PARAMETERS (TA = +25oC) PARAMETERS VIO IBIAS IIO DELTA LIMITS 2.0mV 75nA 75nA
TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS CONFORMANCE GROUP Initial Test Interim Test PDA Final Test Group A (Note 1) Subgroup B5 Subgroup B6 Group D Group E, Subgroup 2 MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 Sample 5005 TESTED FOR -Q 1, 9 1, 9, 1, 2, 3, 10, 11 1, 2, 3, 9, 10, 11 1, 2, 3 1 1 1 1, 2, 3 RECORDED FOR -Q 1 1,
NOTE: Alternate Group A testing may be exercised in accordance with Method 5005 of MIL-STD-883.
Spec Number 5
518855
HS-2420RH Test Circuits
VDC ALL RESISTORS = 1% ALL CAPACITORS = 10%
100k 10k +VCC -VCC S/H
2
S2
1
1
2
S7
A
1 S4 2 3 100k + NULL AMP X1 X-1 BUFFER
DUT GND S5 2 1 OPEN
-
50 2 1 S1 2 S6 50
1 2
S7
+
1
CH = 1000pF
S3 3
1 50pF
2k
+VCC 1M VAC 50 + ILOAD
-
AOUT 4 3 EOUT S8 1 2
FIGURE 1. TEST FIXTURE SCHEMATIC (SWITCH POSITIONS S1 - S8 DETERMINE CONFIGURATION)
+5V SINEWAVE INPUT IN2 IN1 IN3 IN4 IN5 IN6 IN7 IN8 A2 A1 EN +15V -15V +15V -15V
OUT VIN
+ DUT 2k CH = 1000pF
-
VOUT 50pF 50
DUT + 2k S/H CH = 1000pF
-
VOUT 50pF
A0
SAMPLE/HOLD CONTROL INPUT
NOTE: Compute Hold Mode Feedthrough Attenuation from the Formula: VOUT HOLD FeedthroughAttenuation = 20 log ---------------------------------- VIN HOLD - Where VOUT HOLD = Peak-Peak Value of Output Sinewave during the Hold Mode. FIGURE 2. HOLD MODE FEEDTHROUGH ATTENUATION
GBWP is the Frequency of VINPUT at which: VOUT 20 log --------------------- = - 3dB VINPUT
FIGURE 3. GAIN BANDWIDTH PRODUCT
Spec Number 6
518855
HS-2420RH Test Circuits (Continued)
SEND SAMPLE COMMAND
SET t2 TO 7s INITIALLY
COURSE tACQ MEASUREMENT LOOP
FINE tACQ MEASUREMENT LOOP
DIGITIZE V1 AT t1 (10s)
INCREMENT t2 BY 50ns (50ns LONGER DELAY)
DIGITIZE V2 AT t2
DECREMENT t2 BY 50ns
DIGITIZE V1 AT t1 (10s) CALCULATE V1 - V2 IS V 0.01%? YES DIGITIZE V2 AT t2
NO DECREMENT t2 BY 50ns RECORD tACQ
YES CALCULATE V1 - V2 IS V 0.01%?
NO
NOTE: See Test Diagram, Timing Diagram FIGURE 4. ACQUISITION TIME (tACQ TO 0.01% IS SHOWN, tACQ TO 0.1% IS DONE IN THE SAME MANNER)
t1
HS-2420RH
V1 V1 DIGITIZER
+ +10V 0V OR 0V -10V S/H CONTROL
+ 50pF 2k 1000pF t1 V2 V2 DIGITIZER
COMPUTER CONTROLLER
DELAY t2 VARIABLE DELAY
10s
t2 DELAY CONTROL
FIGURE 5
Spec Number 7
518855
HS-2420RH Timing Waveforms
10V VIN (POS tACQ CASE)
0V 2V 0.01% OR 0.1% ENVELOPE 10V
S/H CONTROL
0V
DUT OUTPUT (POS tACQ CASE)
0V t1 10s (t1 DIGITIZER COMMAND)
t1 (t2 DIGITIZER COMMAND) t2 t2
FIGURE 6. TIMING DIAGRAM FOR ACQUISITION TIME, (POSITIVE tACQ CASE)
VPEAK +V 0V 90% VFINAL 10%
INPUT 10% 0V +OS, tR -OS, tF -V tR tF 90% VFINAL VPEAK
FIGURE 7A
FIGURE 7B
FIGURE 7. OVERSHOOT, RISE AND FALL TIME WAVEFORMS
+V +V +V 75% INPUT 25% -V -V +SL -SL -V t t 75% -V +V 25%
FIGURE 8A FIGURE 8. SLEW RATE WAVEFORMS
FIGURE 8B
Typical Performance Curves
1000 DRIFT DURING HOLD AT +25oC mV/s
VSUPPLY = 15VDC, TA = +25oC, CH = 1000pF, Unless Otherwise Specified
1000 LOWER 3dB FREQUENCY = 10Hz OUTPUT NOISE "HOLD" MODE
100 UNITY GAIN PHASE MARGIN (DEG) 10 HOLD STEP OFFSET ERROR (mV) 100 mV RMS
1.0
EQUIV. INPUT NOISE "SAMPLE" MODE - 100K SOURCE RESISTANCE 10 EQUIV. INPUT NOISE "SAMPLE" MODE - 0K SOURCE RESISTANCE 1 10
0.1
UNITY GAIN BANDWIDTH (MHz) MIN SAMPLE TIME SLEW RATE/ FOR 0.1% ACCURACY CHARGE RATE 10V SWINGS (ms) V/(ms) 100pF 1000pF 0.01mF 0.1mF 1.0mF
0.01 10pF
100
1K
10K
100K
1M
CH VALUE
BANDWIDTH
FIGURE 9. TYPICAL SAMPLE AND HOLD PERFORMANCE AS A FUNCTION OF HOLDING CAPACITOR
FIGURE 10. BROADBAND NOISE CHARACTERISTICS
Spec Number 8
518855
HS-2420RH Typical Performance Curves
1000 OPEN LOOP VOLTAGE GAIN (dB)
VSUPPLY = 15VDC, TA = +25oC, CH = 1000pF, Unless Otherwise Specified (Continued)
100 80 60 40 20 0 -20 -50 -25 0 +25 +50 +75 TEMPERATURE (oC) +100 +125 10 100 1K 10K 100K FREQUENCY (Hz) 1M 10M 100M CH = 1.0F CH = 0.1F CH = 0.01F CH = 100pF CH = 1000pF
100 ID (pA) 10
1
FIGURE 11. DRIFT CURRENT vs TEMPERATURE
FIGURE 12. OPEN LOOP FREQUENCY RESPONSE
-30 -40 -50 -60 -70 -80 -90
OPEN LOOP PHASE ANGLE (DEGREES)
0 20 40 60 80 100 120 140 160 180 200 220 240 10 100
CH = 0.01F CH =1000pF
CH = 1.0F CH = 0.1F
ATTENUATION (dB)
CH 100pF
100
1K
10K
100K
1M
10M
1K
10K
100K
1M
10M
100M
10V SINUSOIDAL INPUT FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. HOLD MODE FEEDTHROUGH ATTENUATION CH = 1000pF
FIGURE 14. OPEN LOOP PHASE RESPONSE
Burn-In Circuit
HS-2420RH CERAMIC DIP
-IN +IN OFF ADJ OFF ADJ -V NC OUT S/H CTL 14 GND 13 NC 12 HOLD CAP 11 NC 10 +V NC +15V 9 8 D1 C1
Irradiation Circuit
1 2 R1 3 4 -15V 5 C2 D2 6 7
1 R 2 GND 3 4 V2 5 6 7
14 13 12 GND 11 10 9 8 V1
NOTES: R1 = 100k 5% (per socket) C1 = C2 = 0.1F (one per row) or 0.01F (one per socket) D1 = D2 = 1N4002 or equivalent (per board)
NOTES: V1 = +15V V2 = -15V R = 100k
Spec Number 9
518855
HS-2420RH
HOLD STEP VOLTAGE (V) +10 V+ +5 -10 -5 +5 +10 CH S/H CONTROL
-5 -10
DC INPUT VOLTAGE (V) CH = 0.1F CH = 10,000pF + HS-2420RH + -
-15 -20 -25 -30 -35
CH = 1000pF
-IN CH = 100pF
+IN
V-
OUT
100k OFFSET TRIM (25mV RANGE)
FIGURE 14. HOLD STEP vs INPUT VOLTAGE
FIGURE 15. BASIC SAMPLE-AND-HOLD (TOP VIEW)
0.002RF RF
INPUT +IN HS-2420RH OUT OUTPUT
INPUT RI -IN HS-2420RH OUT +IN S/H CONTROL RI OUTPUT
-IN RF
S/H CONTROL
S/H CONTROL INPUT
0.002RI S/H CONTROL INPUT -RF GAIN ~ RI GAIN ~ I + -RF RI
FIGURE 16. INVERTING CONFIGURATION
FIGURE 17. NONINVERTING CONFIGURATION
Offset and Gain Adjustment
Offset Adjustment The offset voltage of the HS-2420RH may be adjusted using a 100k trim pot, as shown in Figure 15. The recommended adjustment procedure is: 1. Apply zero volts to the sample-and-hold input, and a square wave to the S/H control. 2. Adjust the trim pot for zero volts output in the hold mode. Gain Adjustment The linear variation in pedestal voltage with sample-and-hold input voltage causes a -0.06% gain error (CH = 1000pF). In some applications (D/A deglitcher, A/D converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sample-and-hold. The two circuits shown below demonstrate how to adjust gain error at the sample-and-hold. The recommended procedure for adjusting gain error is: 1. Perform offset adjustment. 2. Apply the nominal input voltage that should produce a +10V output. 3. Adjust the trim pot for +10V output in the hold mode. 4. Apply the nominal input voltage that should produce a -10V output. 5. Measure the output hold voltage (V-10 NOMINAL). Adjust the trim pot for an output hold voltage of
( V-10 NOMINAL ) + ( - 10V ) --------------------------------------------------------------------------2
Spec Number 10
518855
OFFSET ADJUST V+ R1 Q23 Q58 Q64 Q29 Q2 Q66 Q45 Q59 Q46 Q72 Q4 Q30 Q65 R2
Schematic
Q17
Q5
Q106
R3
RP Q15 Q6 Q48 Q27 R7 Q50 Q31 Q19 Q25 Q18 Q101 Q22 Q26 Q35 Q56 Q55 Q38 Q100 Q60 C4 Q33 Q34 Q20 Q24 Q32 Q53 Q54 Q21 Q51 Q52
Q7 Q28 C2
Q9
R5
Q105
Q73
Q74 CH
Q11
Q8
C3 15pF
Q75 R9 R8 OUT R10 C5 Q77 Q76 Q67 Q68 Q69
Q3
Q10
Q13
S/H CTL
HS-2420RH
11
Q39 Q40 Q41 Q57 Q42 Q43 Q44 R13 IN+ IN-
GND
Q12
Q14
R11 Q78
Q103
Q70 Q63 Q102 Q62 Q71
Q79
Q16
Q80 R14 Q81
Spec Number
V-
518855
HS-2420RH Intersil Space Level Product Flow -Q
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) (Note 1) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Die Attach 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A CSI and/or GSI Pre-Cap (Note 7) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization
NOTES: 1. Modified SEM Inspection, not compliant to MIL-STD-883, Method 2018. This device does not meet the Class S minimum metal step coverage of 50%. The metal does meet the current density requirement of <2E5A/cm2. Data provided upon request. 2. Failures from subgroup 1 and deltas are used for calculating PDA. The maximum allowable PDA = 5%. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B test, Group B samples, Group D test and Group D samples. 6. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group D generic data. Generic data is not guaranteed to be available and is therefore not available in all cases. 7. CSI and/or GSI inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for CSI Pre-Cap inspection, CSI Final Inspection, GSI Pre-Cap inspection, and/or GSI Final Inspection. 8. Data Package Contents: Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. GAMMA Radiation Report. Contains Cover page, disposition, RAD Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. X-Ray report and film. Includes penetrometer measurements. Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). Lot Serial Number Sheet (Good units serial number and lot number). Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. Group B and D attributes and/or Generic data is included when required by the P.O. The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
100% Initial Electrical Test (T0) 100% Static Burn-In, Condition A, 240 Hours, +125oC or Equivalent, Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% PDA, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic (X-Ray), Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) Sample - Group B, Method 5005 (Note 5) Sample - Group C, Method 5005 (Notes 5, 6) 100% Data Package Generation (Note 8) CSI and/or GSI Final (Note 7)
Spec Number 12
518855
HS-2420RH Metallization Topology
DIE DIMENSIONS: 97 mils x 61 mils x 19 mils METALLIZATION: Type: Al Thickness: 16kA 2kA GLASSIVATION: Type: Silox Thickness: 14kA 2kA WORST CASE CURRENT DENSITY: 2.0 x 105A/cm2 TRANSISTOR COUNT: 78 PROCESS: Bipolar-DI
Metallization Mask Layout
HS-2420RH
-IN (1) S/H CONTROL (14)
+IN (2)
(13) GND
OFF ADJ (3)
OFF ADJ (4)
(11) HOLD CAP
V- (5) (7) OUT (9) V+
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 13
518855

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